This is an old revision of the document!
Jonathan “Lord Nightmare” Gevaryahu is a contributor to MESS, mostly in the forms of new dumps, new information, the occasional skeleton driver, and near constant IRC 'verbal diarrhea' commentary that drives MooglyGuy insane.
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Device | Announced | Synthesis | Process | Voltage | Pin | Internal | Minimum | Bit rate | Exciting | D/A |
---|---|---|---|---|---|---|---|---|---|---|
(Factory) | Algorithm | Supply | ROM (bit) | Configuration | (Kb/sec) | Source | (bit) | |||
HD38880B (Hitachi / NTT) | 1979.1 | PARCOR | PMOS | 5 | 28 | — | 3 chips | 2.4-9.6 | Sin²wt, M-array | 8 |
HD61885 (Hitachi) | 1981. | PARCOR | CMOS | 5 | 28 | 32 K | 1 chip | 2.5-9.9 | integrated pulse, M-array | 9 |
MN6401 (Matsushita) | 1980.2 | PARCOR | NMOS | 5 | 28 | 32 K | 1 chip | 1.2-5.5 | Residual segment, M-array | 8 |
MN1261 (Matsushita) | 1980.12 | PARCOR | CMOS | 5 | 24 | — | 3 chips | 2.0-9.6 | Residual segment, M-array | 10 |
M58817AP (Mitsubishi) | 1980.8 | PARCOR | PMOS | - 10 | 28 | — | 3 chips | 1.96-3.92 | Pulse, M-array | 7 |
VSY100 (Sanyo) | 1980. | PARCOR | NMOS | 5 | 40 | — | 2 chips | 2.4-9.6 | Pulse, M-array | 7 |
TMS5100 (TI) | 1978.6 | PARCOR | PMOS | - 9 | 28 | — | 3 chips | 0.6-2.4 | Sin²wt, M-array | 7 |
SP0256 (GI) | 1980.1 | PARCOR | NMOS | 5 | 28 | 16 K | 1 chip | 0.7-2.4 | Pulse, M-array | 7 |
MB8760 (Fujitsu) | 1980. | PARCOR | NMOS | 5,12 | 28 | — | 3 chips | 2.4-9.6 | Pulse, Triangular, M-array | 10 |
T6721 (Toshiba) | 1981.10 | PARCOR | CMOS | 5 | 42 | — | 3 chips | 2.4-9.6 | Residual segment, M-array | 9 |
ECL1565 (NTT) | 1979.10 | LSP | CMOS | 5 | 64 | — | 3 chips | 1.2-9.6 | Pulse, M-array | 8 |
µPD7752C (NEC) | 1981.10 | FORMANT | CMOS | 5 | 28 | 32 K | 1 chip | 2.4-5.6 | Pulse, M-array | 9 |
µPD7751C (NEC) | 1981.3 | ADPCM | NMOS | 5 | 40 | — | 4 chips | 14-20 | ext | |
MSM6502RS (OKI) | 1981.10 | ADPCM | CMOS | 3-5 | 18 | 144 K | 1 chip | 10-32 | 10 | |
LRN3680 (Sharp) | 1980.3 | Composite Sine | CMOS | 4-5 | 44 | 32 K | 1 chip | 1.6 | 8 | |
SPC (NS) | 1980. | Speech segm | NMOS | 7-11 | 40 | — | 2 chips | 2 | ||
µPD1774C (NEC) | 1981.10 | Speech segm | NMOS | 4.5-6.6 | 28 | 48 K | 1 chip | 1-5 | 9 |
Source: Speech Science and Technology pg. 367
Title: Speech Science and Technology Editor: Shuzo Saito Edition: illustrated Publisher: IOS Press, 1992 ISBN: 4274075818, 9784274075810 Length: 380 pages Page: 367